Timing violation, from clock to data

I should have specified the device, sorry about that. This is running on a Cyclone 5CGX.

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Internal clocks can use this, not just PLL outputs.

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I think this isn't true, at least for my device, I don't know about others. Only certain clocks can go into the clock-control multiplexer according to the documentation, this is the relevant part (summarized from CycV handbook vol1, table 4-6 on version 2016.06.10):

• inclk
• inclk
• inclk

If you try to connect it differently it just doesn't compile.

I really want to avoid having to post my sdc file because it's going to take me a _long_ time to strip it down, it's actually multiple files with lots of variables and constants. I'll do it if needed though, of course, but I want to ask you about one thing before I go down that road.

I already have a generated clock for each clock after the mux and they're all excluded from one another. My timing violation is about the source clock (PLL) being used as the source node for the output pin (target node). I think this is related to your last comment

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... and a false path constraint on that path as well (so the output clock path is not analyzed as a data path)

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do you mind explaining this in a bit more detail please?

Thanks!