Timing violation, from clock to data

I don't understand this statement: "I can't use the CLKCTRL internal clock mux because all the clock sources are internal." Just add the clock control block as an IP to your design. Internal clocks can use this, not just PLL outputs.

You need set_clock_groups exception(s) to isolate the clocks going into the mux (use the -exclusive option, though that doesn't really matter). Only one clock can come out of the mux at a time so you need to tell the tool this.

You also need a generated clock on the output clock pin with the source as the output of the PLL and the target as the output pin (port) of the device. The timing analyzer see outputs as data paths, not clock paths, so you need this extra generated clock and a false path constraint on that path as well (so the output clock path is not analyzed as a data path).

It might be helpful to show your current .sdc file.