Honored ContributorHi everybody!
Does anyone know how I can perform timing simulation using modelsim. I have downloaded Quartus II 9.1 free suscribtion edition and free modelsim from altera website. I have a very simple design: an input port, not gate and output port. I want to see the delay between ports in modelsim wave. How can I do that?? Thanks for answers!!!
Honored ContributorSorry I cant help here - I never run gate level sims (RTL simulations and timing analysis are all you need 99.99% of the time - 10+ years in industry, never needed a gate level sim).
Why are you trying a gate level simulation? if you are relying on gate delays for timing, then you are going to run into problems. Gate level sims will only show the worst case, and in reality the timing will vary.Honored ContributorTricky,
I'm new to Altera (my past experience has been with Xilinx), so I'm just trying to learn Quartus and Modelsim. My method of "climbing the learning curve" is to try something and see if the results are what you would expect. I've read that a gate level sim. is supposed to show actual gate delays, but I'm not seeing it. No particular reason I need to do a gate level sim., other than it is part of the learning process. TonyHonored ContributorHello, I am having problems with a ModelSim simulation of a program. The signals I want to simulate (with a RTL simulation) change their logic state in microseconds and I cant find the way to change the timing of the simulation. I tried to change it to 100 us and the simulation stops in 20000 ps so I cannot see anything. How can I increase the time of simulation in ModelSim
Honored Contributorfrom the tcl consol, you can type how long you wish to run:
run 100 us If it doesnt run for this long, there is a problem with the code/testbench.Honored ContributorYes, I think that is the problem, I will try to fix it. This is the first time I have this problem. I will re-think the testbench code, thanks Tricky.
Honored Contributorif you post the code, maybe we can help?
Honored ContributorHi Tony,
May I know what device that you were using? If you were using V series device, gate level simulation is not supported. Gate level simulation is supported on IV series and lower, and you will had to use *.sdo for it. Usually, gate level simulation will be very slow for verification. user should use time quest instead for timing analysis. Thanks, Best regards, Kentan (This message was posted on behalf of Intel Corporation)
