Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi Tony,
May I know what device that you were using? If you were using V series device, gate level simulation is not supported. Gate level simulation is supported on IV series and lower, and you will had to use *.sdo for it. Usually, gate level simulation will be very slow for verification. user should use time quest instead for timing analysis. Thanks, Best regards, Kentan (This message was posted on behalf of Intel Corporation)