timing simulation with modelsim-altera

Tricky,

I'm new to Altera (my past experience has been with Xilinx), so I'm just trying to learn Quartus and Modelsim. My method of "climbing the learning curve" is to try something and see if the results are what you would expect. I've read that a gate level sim. is supposed to show actual gate delays, but I'm not seeing it. No particular reason I need to do a gate level sim., other than it is part of the learning process.

Tony