Honored ContributorHi everybody!
Does anyone know how I can perform timing simulation using modelsim. I have downloaded Quartus II 9.1 free suscribtion edition and free modelsim from altera website. I have a very simple design: an input port, not gate and output port. I want to see the delay between ports in modelsim wave. How can I do that?? Thanks for answers!!!
Honored ContributorHi,
you need to setup the NativeLink in Quartus to use ModelSim as the simulator, write a testbench. To set it up, go to Assignments -> EDA Tools Setting -> Simulation Then you can invoke ModelSim directly from Quartus Tools -> Run EDA Simulation Tool For details, look into the Quartus II handbook, there's a Chapter about ModelSim.Honored ContributorFist, thank's for the answer. I have performed timing simulation with modelsim-altera.
But I can see just my code "ports" waves behavior. I want to check for instance the delay between a logic gate input "port" and the output "pin" of this logic gate. How I can do that in modelsim? Thanks for answers :)Honored ContributorHi, I'm having touble with the PowerPlay tool in Quartus II. I'm a beginner to this software. I have generated the reqd vwf , vcd and saf files but when i run the PowerPlaytool i keep getting an error saying ' Successful run of Assembler reqd' . I the run the fitter and assembler from the processing/start menu , but i still receive the same error. I would be greatful if you could help me .
Thank You.Honored ContributorHi shalom,
I saw your post.I am as novice as you were when you had postedd this . I need to carry out a worst case delay analysis for my verilog design. I ahve compiled my deisgn and simulated it in altera modelsim.I can observe the delays in my waveform ouput.But I need to measure theprecise delay . Is therre any seting in the modelsim to obtain the timing analysis report? Please share them as soon as possible.Honored ContributorInstead of relying on a delay (gate-level) simulation, use the TimeQuest timing analyzer along with your RTL simulation to verify your design. This is much easier to setup and use than a gate-level sim.
Honored ContributorIf you are checking the timing simulation to ensure delays are "what you expected", there is probably something wrong with your design
Honored ContributorHi all,
I have a question related to this thread. When I run a gate level simulation, I never see gate delays in the Wave view. As an example, I created an 8 bit counter, and expected to see some delay from rising clock to the Q outputs. But the output transitions line up precisely with the clock transition no matter how tight I zoom in. Question: should I see typical delays that would be present in the physical device? Are there settings somewhere that I need to change? Thanks! TonyHonored ContributorSounds like you're running an RTL simulation, not a gate level one.
Honored ContributorTricky, well I click on the "Gate Level simulation" toolbar button in Quartus, and still not seeing any delays in the waveforms. Is there any other setting I need to make to insure a true gate level simulation? Thanks.
Honored ContributorAny ideas why I'm not seeing gate delays when I run a gate level simulation??? Thanks.
