timing simulation with modelsim-altera

Hi all,

I have a question related to this thread. When I run a gate level simulation, I never see gate delays in the Wave view. As an example, I created an 8 bit counter, and expected to see some delay from rising clock to the Q outputs. But the output transitions line up precisely with the clock transition no matter how tight I zoom in. Question: should I see typical delays that would be present in the physical device? Are there settings somewhere that I need to change?

Thanks!

Tony