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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timing Simulation Quartus9.1sp1

Hallo all there, i have a question concerning the Timing Simulation in Quartus. In Quartus, via Assignements > settings > EDA Tool Settings > simulation i chose ModelSim as the tool, ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ok,

so for a big project (including a NIOS Processor, and many IP Cores) it is not possible, i can only let create a TB-File for my Top Level File which instantiates the Top as a Device Under Test, the rest should be written by myself.

thanks a lot for your help