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Honored Contributor
Honored ContributorTiming requirement not met?
Could anyone tell me what causes this happen to my code?
After compilation, I got clk Slack -4.076 and End Point TNS -73.368; All the stuff under the minimum Pulse width:'clk' report is in red...also the same thing for setup summary. Thanks in advance...
module memory(clk,mem_oe,mem_rw,addr,mem_data);
input clk,mem_oe,mem_rw;
//mem_oe=1 for memory output enable, mem_oe=0 output=ZZZZ...
//mem_rw=0 for read, mem_rw=1 for write
input addr;
inout mem_data;
wire mem_data;
reg ram;
reg data_out;
//integer i;
assign mem_data = (!mem_rw&&mem_oe) ? data_out : 18'bz;
always@(posedge clk)
begin
if(!mem_rw) // read from the memory
begin
data_out<=ram;
end
else // write to the memory
begin
ram <= mem_data;
end
end
endmodule
