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After the compile, run TimeQuest. Double click "Report Clocks" and make sure your clock frequency is what you specified it to be. You can also run "Report Unconstrained Paths" and if your clock is not constrained, it will show up there. I am assuming you constrained your clock. If you did not, create a .sdc file to constrain the clock.
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Hi,
I assume that you run the simulation with your RTL code. This simulation did not take into account any delay which you will have later on when the design is implemented in the FPGA. What you test with this simulation is the function of your design. But in the FPGA you will delays between your registers ( routing delay and cell delay). These delays limits
the maximum frequency which you can use running your design. You always constraint your clocks, because Quartus needs this for opitimizing your design in the right way.
Kind regards
GPK
Honored Contributor
