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Altera_Forum
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15 years ago

Timing problems, and calculating max and min input delays...

Hi all... Another day, another problem... Before I start I should say that I am using the FTDI Morph-IC-II board, which has a Cyclone II EP2C5F256C8 FPGA and an FT2232H Usb bridge, Quart...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Great!

Good thing that you found the logic bug, I had simulated your design and could see nothing wrong with the input timing.

Regards,

Josy