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Altera_Forum
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15 years ago

Timing problems, and calculating max and min input delays...

Hi all... Another day, another problem... Before I start I should say that I am using the FTDI Morph-IC-II board, which has a Cyclone II EP2C5F256C8 FPGA and an FT2232H Usb bridge, Quart...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

YAY!...all is working now as expected....

I just had one extremely stupid error, which meant that that ROU0 to ROUT23 went to 0 when their input registers were reset, but H_Sync (ROUT18) and V_Sync (ROUT19) needed to be reset to 1 as if it was 0 it satisfied some other logic conditions when they shouldn't; which lead to reading the wrong things at the wrong times and loosing data bytes....

cheers for all your help. I am a very happy guy now, and my first real FPGA design works!

Regards,

Lee H