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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timing problems, and calculating max and min input delays...

Hi all... Another day, another problem... Before I start I should say that I am using the FTDI Morph-IC-II board, which has a Cyclone II EP2C5F256C8 FPGA and an FT2232H Usb bridge, Quart...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think I may have found the problem... and its with the logic in my design... which is typical! another noob error.... I will let you know whether correcting it fixes the problem... but I foolishly reset something which is active low to '0' rather than to '1'.......

Hopefully this will fix it....