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Altera_Forum
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15 years ago

Timing problems, and calculating max and min input delays...

Hi all... Another day, another problem... Before I start I should say that I am using the FTDI Morph-IC-II board, which has a Cyclone II EP2C5F256C8 FPGA and an FT2232H Usb bridge, Quart...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Lee,

I estimated that even without constraining the inputs the design wouldn't have any difficulty as a Tros and Troh of about 12 ns is very generous.

Could it be so simple that the switch-position on the deserialiser board that sets the active edge of the receive clock (RFB on S1) is wrong?

If all else fails would you send me a .qar of the project?