Honored Contributor
Honored ContributorThank you very much once again...
I think I understand the skew approach, but the system approach does seem to be easier... I am pretty sure I understand it now, It was just getting my head around how tCO and tCOmin was the hard part, and that diagram really helped... I have constrained my input timing as you suggested but seem to still be getting some timing issues somewhere, as my the logfiles seem to be missing some bytes. I was clocking my data (ROUT0 to ROUT23) into input registers using the RCLK from the deserialiser board. The RCLK is put through a PLL to give me a clock (MULT_CLK) that is 4xRCLK but is synchronous with it. The 2nd, 3rd and 4th rising edges of MULT_CLK are used to load the 8 of the 24 bits of data into an 8bit wide DCFIFO, the 1st rising edge of mult clock is not used as this occurs at the same time as the rising edge of RCLK, which is when the data changes, and is not used to aviod any race conditions or reads before the next byte has arrived. I am assuming that there are no timing problems with the other end of my FIFO as before connecting the deserialiser board I was using an 18bit counter, with the real RCLK, H_sync (ROUT18) and V_SYNC(ROUT19) and some null values for the 4 reserved bits. The logic and timing in that design works properly, with no lost bytes etc. However when using the actual LVDS data rather than the counter I appear to be loosing some bytes, which makes me think I still have a timing problem somewhere still? My SDC constraints are in the attached .txt document, as this post was over the character limit when I tried to paste it in! Any ideas are very welcome as I can't see where I am losing these bytes!? Regards, Lee H
