Lee,
Hope a picture is worth that thousand words.
As the clock is produced by the device that also produces the data, you have a source synchronous set-up and you do not have to consider the actual size of the delays but only the differences between the delay of the clock signal and the other (data) signals. That leaves us
- External device tCO (tCO_ext)
- External device tCOmin (tCOmin_ext)
- Largest positive difference of delays between clock and data (latest arrival)
- Largest negative difference of delays between clock and data (earliest arrival)
Input delay max = tCO_ext + largest_positive_skew_data_to_clock
Input delay min = tCOmin_ext + largest_negative_skew_data_to_clock = tCOmin_ext - abs( largest_negative_skew_data_to_clock )
tCO_ext = Tcyc - Trosmin
tCOmin_ext = Trohmin
I feel more comfortable using this approach than the skew approach, and leave it to others to explain the skew approach.
Honored Contributor
