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The receive clock comes along with the received data over the loom, so the length of the loom has no influence and you can apply the 'source-synchronous' constraint rules for SDR data with a centre aligned clock. Assuming that all signal lengths are reasonably equal we can forget about them. Else you have to add the largest positive difference in travel-time compared to the clock to the TcoMax and likewise add the largest negative difference in travel-time relative to the clock from the Tcomin (effectively making it smaller)
I opened up the DS90C124 datasheet on National's web-site.
On page 11 and pages 4 and 5, you can see that you get a minimal of 40% of Tcyc as both hold and setup times. You can either translate this in skew or in TcoMax and Tcomin values.
Translating it in to Tco: Tcomin is 40% of Tcyc ( = Troh) and TcoMax is then 60% of Tcyc ( = Tcyc - Tros)
# set frequency in MHz
set FreqRClk 25.0# calculate cycle time in ns
set Tcyc # and create the clock
create_clock -name RClk -period $Tcyc RClk # calculate the min and max delay
set Tcomin
set TcoMax # and apply
set_input_delay -clock RClk -max $TcoMax RxD
set_input_delay -clock RClk -min $Tcomin RxD
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Hi josyb,
Thanks for all of your help. I am trying to make sure I understand how to calculate these things for future reference.
Using the system centric approach, the required information would normally be
- Max and min data path delays
- Max and min clock path delays
- External device tCO (tCO_ext)
- External device tCOmin (tCOmin_ext)
And the input delays can be calculated using:
Input delay max = <Max data delay> + tCO_ext - <min clk delay>
and
Input delay min = <Min data delay> + tCOmin_ext - <max clk delay>
These data and clock path delays from what you say I am assuming are all external to the FPGA, i.e. the delays in the external device and loom which connects to the input pins of the FPGA. And we are making the assumption that these are all equal? Which would give:
Input delay max = tCO_ext
and
Input delay min = tCOmin_ext
I can see from your code that to work out the tCO and tCO min you used
tCO_ext = tCLK - tROS
tCOmin_ext = tROH
but where does this come from?????
I then tried to look at the skew approach (FPGA centric) and I found the following equations:
Data Valid Window = UI - 2 * tSKEW
which for clock centred sampling would mean that
tSU_fpga = tH_fpga = 1/2 * Data Valid Window
and from that:
Input delay max = tCLK - tSU_fpga
Input delay min = tH_fpga
I was just slightly confused by this, as this seems to be a very similar equation to the tCO calculations except using the setup and hold times for the fpga rather than the external device.... I think I am just looking for some clarification/further understanding of how the tCO and tCOmin are calculated, and to confirm that we can definately ignore any other board/clock delays????
Cheers for any help on this... It's just one thing to be given an answer and another to understand why it is the answer!
Regards,
Lee H
Honored Contributor
