Timing Problem(Clock Edge)

thanks for all ur comments. i hav finished modifying de traffic code and now it is really works.. sorry if i bother u all too much..

another question.. de prob that i facing now is that i want to generated a 1 Hz clock using clock divider method from the original crystal frequency of 33.333 MHz.. The FPGA board that I'm using is Apex20k EFC200-484 from Altera

de code is as below :

begin

cloc:process(clk)

variable cnt : integer range 0 to 16500000;

begin

if(clk'event and clk='1') then

if(cnt=16500000)then

cnt:=0;

clkout<='1';

else

cnt := cnt+1;

clkout<='0';

end if;

end if;

end process cloc;

I had compiled the code above.. and when i simulate for 2 seconds .. it took me overnite to finish .. anyone hav better idea than this method? thanks