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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timing Problem(Clock Edge)

Dear all, I'm new to VHDL and need all u guys out there, I'm currently designning a VHDL code for traffic light (two processes) coding style and i bump to this error regarding clock timing...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hello,

If you post your new code in a file it is easier to help you directly. Otherwise I would suggest you look in the simulation and try to find the root of your problem. First check the clock and reset you generate in your testbench. If it still does not work you will have to start from the top and work yourself down until you find the problem. I know it's easier said then done but you will learn a lot more from that then someone telling you what is wrong.

Best Regards,

Ola Bångdahl