Timing Optimized VHDL Code

This comes down to fundamental understanding - you're going to have to find textbooks on basic digital logic hardware and read a good VHDL tutorial that shows you the templates for basic elements and shows you designs - I think this often gets good reviews:

https://www.amazon.co.uk/designers-guide-vhdl-systems-silicon/dp/0120887851/ref=pd_sim_14_3?ie=utf8&dpid=41hoxajjmtl&dpsrc=sims&prest=_ac_ul160_sr116%2c160_&refrid=dh37pjhmb0pwzwt3xz68

But there are many many out there.

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At this point I never thought past RTL code, besides maybe that a clocked process is something like a flip flop.

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In a clocked process, every bit of every signal assigned in the becomes a single flip flop. The if/elseif/else statements make the combinatorial logic.

So the more layered ifs, the longer the logic chain. (this is a very crude analogy, but you will need to understand what logic your code is generating.

So see the generated output - you need the RTL and map viewers, available in Quartus via Tools->Netlist Viewers.