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Altera_Forum
Honored Contributor
Honored ContributorTiming Optimized VHDL Code
I'm looking for coding guidelines, rules, online resources, examples, etc. on how to write VHDL code that helps me achieve a higher fmax for my FPGA design. Does anybody have any good recommend...
Altera_ForumHonored Contributor
Honored ContributorIncreasing the FMax of a design is all about decreasing the routing delay between two registers. Routing delay is primarily increased by logic (ie. LUTs). If you understand how your code is mapping to logic and registers, then it is simply a case of modifying your code to reduce the logic and adding more pipeline stages. Its not about knowing specific coding examples, as every situation is different.
I would suggest understand how your code maps to logic first before reading up how to increase FMax as you will not understand the 2nd problem without understanding the first.
