Forum Discussion

ENava's avatar
ENava
Icon for New Contributor rankNew Contributor
3 years ago

Timing of a parallel bus in a source synchronous interface

Hi all! I'm testing an interface between a CycloneIV fpga and a AD9915 DDS, and I observe random mishaps. This is an extract of AD9915 datasheet: When DDS is in parallel mode (selected via...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Let me know if you have any further concern or update.


Thanks,

Best regards,

Sheng