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ENava's avatar
ENava
Icon for New Contributor rankNew Contributor
3 years ago

Timing of a parallel bus in a source synchronous interface

Hi all! I'm testing an interface between a CycloneIV fpga and a AD9915 DDS, and I observe random mishaps. This is an extract of AD9915 datasheet: When DDS is in parallel mode (selected via...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

I miss the constraint set_multicycle_path. This constraint most probably suits your case better. Checks this video (10:53) for further details.

For example before set_multicycle_path (image),

After set_multicycle_path (image),

Thanks,

Best Regards,

Sheng

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