New Contributor
Super ContributorHi,
Here is the SDC collections link https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#tafs/tafs/tcl_pkg_sdc_ver_1.5.htm. May be the SDC constraints below can help you out:
set_max_delay
set_min_delay
set_data_delay
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorI've tried set_max_delay and set_min_delay, but I can't understand how they work.
#**************************************************************
# Set Maximum Delay
#**************************************************************
set_max_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_data_out[1][*]}] -to [get_ports {dds_data[*]}] 12
set_max_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_func_out[1][*]}] -to [get_ports {dds_function[*]}] 12
#**************************************************************
# Set Minimum Delay
#**************************************************************
set_min_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_data_out[1][*]}] -to [get_ports {dds_data[*]}] 11.5
set_min_delay -from [get_registers {dds:dds_inst|ad9915:ad9915_inst|sync_func_out[1][*]}] -to [get_ports {dds_function[*]}] 11.5
Per my understandings these should tell the fitter to insert some delay to guarantee 12ns of propagation, and match the spread to 500ps, but this is the result:
Delays have increased *a lot*, ranging from 15.5 to 16.5 ns. Neither min_delay nor max_delay have been satisfied.
What am I missing?
