Timing models don't match measured delays

For all practical purposes, this is my design:

module ghrd_agilex_top (
  input   wire  fpga_clk_100,
  output  wire  master_tod_top_0_pulse_per_second,
  output  wire  master_tod_top_0_pulse_per_second_raw
);

  (* dont_merge *) reg sta_test1;
  (* dont_merge *) reg sta_test2;
  always @(posedge fpga_clk_100 or negedge system_reset_n) begin
    if (~system_reset_n) begin
      sta_test1 <= 1'b0;
      sta_test2 <= 1'b0;
    end
    else begin
      sta_test1 <= ~sta_test1;
      sta_test2 <= ~sta_test2;
    end
  end
  assign master_tod_top_0_pulse_per_second     = sta_test1;
  assign master_tod_top_0_pulse_per_second_raw = sta_test2;
endmodule

Of course the design actually contains a lot more, but it does not affect the issue at hand, which is that the STA for this part does not seem to match the measured results.