Timing models don't match measured delays

How are you gathering the numbers in the table from the TA?  Are you using data arrival times from whatever is driving these registers and from these registers to the output pins?

I guess it's not clear what design you are using and what is actually driving these registers.  Also not clear is your clocking setup.  Are you using a PLL that's driving a global clock resource or are you driving the registers directly?

I think more detail on your setup and how you are getting these numbers is needed.