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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timing issues

Hello all, I am not an expert in FPGA design, so excuse me if I am asking some silly question. In my design, I need to use a a 16bit CRC over a 64bit word. I found one design in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Since you're doing it in 1 clock cycle, that makes sense. (If you were putting in 32 bits and then another 32 bits over two clock cycles, then it would fail). Anyway, put:

set_multicycle_path -setup 2 -to CRC:inst|ucrc_par:PGEN|match_o

set_multicycle_path -hold 1 -to CRC:inst|ucrc_par:PGEN|match_o

set_multicycle_path -setup 2 -to CRC:inst|ucrc_par:PGEN|crc*

set_multicycle_path -hold 1 -to CRC:inst|ucrc_par:PGEN|crc*

This says that there are two clock cycles for the data to get through(basically your ignoring whatever these registers clock in immediately after the data is sent.) If you can wait 3 clock cycles, then change it to 3 and 2 respectively. Note that I haven't disected the design, as you want to be careful to add multicycles only to paths that are true multicycles, or else you may pass timing analysis and fail on the board.