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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timing issues

Hello all, I am not an expert in FPGA design, so excuse me if I am asking some silly question. In my design, I need to use a a 16bit CRC over a 64bit word. I found one design in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Anyway, go to the easics site, put in your polynomial and set the databus width to 64. That means you'll get your result in 1 clock cycle. See what it runs at. If it doesn't meet timing, then set it to 32, so you'll require 2 clock cycles(but it should run much faster). See what you can get.

Also try the cookbook, which should be more optimized, but not as easy to modify.