Timing issues

It's not really "stabilizing", it's pipelining. Since it's a feedback structure, you'd take a couple clock cycles to get your output, and couldn't put a new input into it. So you're not calculating at the line rate.

I would like at some other implementations. In the current one, you have 40 levels of logic with no carry-chains, which won't go near 80Mhz.

Yes, I would trust static timing analysis and meet timing. Not sure why your timing simulation would work unless it's a multicycle, but on anything that feeds back like this, I doubt it. Basically it's saying when data is launched from the source register, it will not make it to the destination register in time, and on the next clock the destination register will clock in some unknown value. Again, I'm surprised your simulation worked. One possibility is that timing sims are exact, so they will calculate the exact same value every time because the delay it uses is exact. But in hardware your delays will vary some, and the CRCs will calculate different values. Just a guess.