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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timing issues

Hello all, I am not an expert in FPGA design, so excuse me if I am asking some silly question. In my design, I need to use a a 16bit CRC over a 64bit word. I found one design in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I don't really need the result in one clock cycle, I could probabaly let it stablize for one or two clock cycle...but just out of curiosity, how fast can I make it running.

yes..I am implementing a transmitter and a receiver, so on both side, I'll have similar CRC structures..

BTW..If my time quest says I have timing issues (setup, hold...), but my timing simulation (both slow and fast mode) suggests that the design is ok. Can I ignore the warning from Time Quest? or I should ALWAYS try to eliminate the warnings by put constrains and others?

Thx