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Altera_Forum's avatar
Altera_Forum
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17 years ago

Timing Issue Need Help

Hi Dears:

There is a project, I constrained the fmax to 500Mhz. It can run above 500mhz after I enable the physical Synthesis Optimization - register retiming. If this optimization not enabled, it just ran at about 330Mhz. I attached the project, could anyone check my source code and point out where is the issue?!

I assumed that there is some code style issue, but i can't suer.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi Dears:

    There is a project, I constrained the fmax to 500Mhz. It can run above 500mhz after I enable the physical Synthesis Optimization - register retiming. If this optimization not enabled, it just ran at about 330Mhz. I attached the project, could anyone check my source code and point out where is the issue?!

    I assumed that there is some code style issue, but i can't suer.

    --- Quote End ---

    Hi Jerry,

    register retiming moves the registers in your design in order to achieve the required clock speed. Look into the attachment to see how it works. Without the feature you have to do this by yourself, which could be very difficult in case you have a complex design.

    Do you have a problem with the retiming feature, e.g. your P&R run takes to long ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi pletz:

    Thanks for your information. I don't have problem about retiming feature currently, but with the design becoming more bigger or complex I do mind the design's performance. So I am finding some way in coding design to settle this issue insdead of tool's optimization.

    Best Regards

    Jerry
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi pletz:

    Thanks for your information. I don't have problem about retiming feature currently, but with the design becoming more bigger or complex I do mind the design's performance. So I am finding some way in coding design to settle this issue insdead of tool's optimization.

    Best Regards

    Jerry

    --- Quote End ---

    Hi Jerry,

    I would use the tool feature, because otherwise you have to specify the register stages by yourself. That could be difficult and could cause some iteration cycles.

    Maybe this could be a way to do it:

    1. Write your design with all registers you need in your design and run P&R.

    Maybe you can add some register stages in front of e.g. blocks with large

    arithmetic functions.

    2. Run a timing analysis and identify your blocks with the longest paths.

    3. Add register stages in front of your identified blocks.

    4. Re-run P&R with retiming enabled.

    When you are using the Megawizard for e.g. divider, multiplier you can specify register

    stages (pipeling) if necessary.

    Kind regards

    GPK