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Altera_Forum's avatar
Altera_Forum
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13 years ago

Timing differences between TimeQuest and gate-level SDF

I'm analyzing a Stratix III design in Quartus 12.0 and am seeing differences in the timing delays reported in TimeQuest versus the SDF back-annotated gate-level netlist. The differences are not large (on the order of a couple hundred picoseconds), but for my design that happens to be critical.

I can see that the SDF back annotation generally lumps interconnect delays with the delay for the cell at the end of the interconnect. But one area where I can't reconcile the differences is around the PLL. Does anyone know if one timing analysis methodology (TimeQuest vs. gate-level SDF) is considered superior?

Thanks,

Jeff

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    It's TimeQuest who analyzes the design and generates the SDF for back-annotation for the gate level simulation.

    If you're seeing an inconsistency, I'd say that either

    a) you're missing something

    b) you've sumbled upon a bug
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks for your insight.

    Based on what you said, it sounds like the ultimate source of the delay information is TimeQuest. Since the TimeQuest reports are also easiest for me to extract the necessary information from, I'll use that data for my analysis.