Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorTiming Constraints with PLL clock muxes
I feed the output of pll to internal fpga logic that drives an output pin. How to constrain the output with respect to the clock input of pll? I am able to constrain w.r.t the output of pll
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorYou may constrain
create_generated_clock -name output_clock -source [get_ports Cb1_clk1] [get_ports clk_out]
