Timing Constraints with PLL clock muxes

Hi,

I want to set output_delay and skew constraints on some output data pins w.r.t the referred clock.

I have 4 input clocks fed to 4 pins of FPGA. They are divided to 2 groups each with 2 clocks fed to 2 pll clock muxes. The out of these pll muxes are fed to one more mux. The final output of this mux is fed to the logic.

Now I am able to constrain w.r.t the output of pll clock muxes.

But I want to constrain my output data pins w.r.t to 4 input clocks that comes to FPGA.

Please refer the figure.I want to constrain w.r.t Cb1_clk1,Cb1_clk2,Cb2_clk1 and Cb2_clk2