Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorTiming Constraints with PLL clock muxes
I feed the output of pll to internal fpga logic that drives an output pin. How to constrain the output with respect to the clock input of pll? I am able to constrain w.r.t the output of pll
sstrell
Super Contributor
Super ContributorIf you are driving out a clock, you'll need a generated clock constraint targeted to that output port. The source of the generated clock will be the output pin of the PLL.
