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JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
6 years ago

Timing constraints when the clock is recovered from data

Hi, I have a serial data stream which arrives at a CPLD pin. This data stream feeds a clock recovery entity which contains a PLL with dynamic phase reconfiguration. The output of the clock recovery ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

If you set false_path assignment to the clock, you will not see the violation in the timing report. If you set false path to the virtual clock and the high frequency sampling clock, the path will not be analyzed and we cannot make sure that the data is sampled correctly.

Thanks.