Timing constraints when the clock is recovered from data

Hi,

here are the files you asked for. I changed the constraints since my original post, but I am still not sure if they are correct.

The part for the re-synchronization circuit start at line:

# Amplifier transmit clock (line 78)

I now define a virtual clock which starts 180 degrees out of phase. I constrain the input data pin AMP_TXD to this clock with a 1 ns margin. This is just a number I assumed to cover for re-synchronization accuracy.

Then I set a false path from this virtual clock to a high frequency sampling clock inside the re-synchronizer. This high frequency clock has the same phase as clk_resync, but 4 times the frequency and is used to sample input data and look for edges.

The timing analyzer does not report any errors for this version.

Regards,

Julia