timing constraints in TimeQuest

if you follow the clock input of inst10 back to the left you end up at the output of inst14

so inst14 "generates" the clock for inst10, well that is a gated clock ... should be avoided

also inst5 is the clock source for inst7

this design is asyncronous, you better do a fully syncronous design where all FFs have the same clock source and you use clock enable functions of the FF instead of gates clocks.

if you (or must) use more more than 1 clock source, use clock crossing circuits

Have a look at the Quartus Handbook Chapter 6 : Recomended HDL Coding Styles

well that is HDL design entry and not schematic design entry as you did, but there might be a documetation for this too.