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Altera_Forum
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10 years ago

Timing constraints for SoC HPS SPIM routed through FPGA fabric

I'm working with a prototype project using an Altera Cyclone V SoC Development kit. We have chosen to route IO pins from one of the HPS SPIMs into the FPGA so that we can put the IOs on the HSMC conn...
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Altera_Forum
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10 years ago

I will try set min/max delay from input pins to output pins. not sure if it is going to be accepted but set max/min input/output delay is likely to be rejected as it is meant for reg to reg path. Just a thought.