Timing Constraints for Serial Interface

Many thanks for your response Brad.

So it seems that its vital to constrain from what you say. This is something I need to expand my knowledge of, as it's not something I have done much of.

I am using the Classic Timing Analyzer at the moment, I have heard that Timequest is quite powerful, but for the moment I am stuck with the classic timing analyzer, although I plan on learning about timequest for the next project.

I am implementing a source synchronous interface and at the moment I don't have any insight into what the FPGA on the other board is receiving. I can only judge by the response if its an error message or the expected data. It's not the ideal situation, but until things get organized it will be that way.

I am placing my constraints using the assignment editor. Is this the correct place to do it? You mentioned about the tsu, th, tco, and minimum tco constraints in the Classic Timing Analyzer, but is this where I should insert the constraint, or are they specified for the whole design in this area. (silly question, but I am a little confused).

Thanks for the explanation on the tco. I hadn't understood this properly. But I have one further question regarding it. In my case I have a 40 MHz clock entering the FPGA, which then enters a PLL where 83 MHz is produced. The 83MHz is then used to clock the logic for the interface and is also sent on the clock line of the interface. So if I set a tco of 3ns for example, how is this 3 ns calculated, would it be based off the 40 of 83MHz. I would want it to be based on the 83MHz, but from its the input clock pin to output pin that confuses me. I'm not sure how it works.

I have had a look at a couple of handbooks but its all a little daunting and its hard to know where to begin. The explanations offered at times I find a little hard to understand. I'm probably lacking a little knowledge in the theory end of things, which I hope will improve with experience.

For a source synchronous interface and using the classic timing anlyzer, which constraints should I be looking to research. There seem to be various which overlap and do similar things.

I have been thinking maybe the best approach would be to send the clock with the chip select and the data delayed slightly, perhaps by 1/3 of a cycle, so that when the the following rising edge is detected on the rxer side, I can be sure that the data is stable.

Is this the correct approach and if so, which types of constraints to I need to apply in the assignment editor. I have been playing around with different one's without really understanding what there are actually doing.

Should I be looking at tsu and th also, how do they affect the operation of the interface, is it sifficient to put the delays.

Please forgive my ignorance, but I really appreciate the help,

Thanks again