Occasional Contributor
Super ContributorWhy do you have two set_max_delay constraints with different values? The second one should be set_min_delay.
Your data required calculation is incorrect. It should be (8.333 + 7.773 - tsu), whatever the setup timing requirement of the input register is.
Your data arrival time calculation is missing the data input delay. It should be (8.263 + 8.302 + 10.368 + 9.817) but that obviously makes things worse. The input and output delays and clock delays are way too big. The input and output registers are getting placed very far from the I/O to have data delays over 8 and 9.
Are you using a PLL? Have you tried using the fast I/O register assignments to use the registers located directly in the I/O cells?
And you're saying the tool still says these I/O are unconstrained?
Occasional ContributorTyped the command twice. The first is the correct one.
Yes, thank you for the corrections. It is even worse than what I originally typed out.
The implementation details are not of importance since I am working on those still. The tool should have certainly caught the timing issues at this point considering such abysmal timing.
The tool does say these I/O are unconstrained.
I'm not sure the set_max_delay command did what I wanted it to do considering it didn't catch this. Any Insight?
set_max_delay -from [get_ports output_port] -to [get_ports input_port] 10.368
