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tmont3's avatar
tmont3
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7 years ago

Timing constraints for asynchronous I/O input pin

What is the right way to constraint an FPGA input pin coming from a analog stage whose last stage is a Schmidt trigger, thus converting the signal to "digital domain"? I'm asking this because some t...
cconger's avatar
cconger
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7 years ago

Also try removing inSignal from the process sensitivity list, I don't think it belongs there:

A_filtering : process(clock, resetb)

begin