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Altera_Forum's avatar
Altera_Forum
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14 years ago

Timing constraints for a feedback clock system

Timing constraints can be tricky... any help in understanding this one is welcome. Please read the word document and take a look at the timing contraints and reports. The question to me is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Here is the stripped project... and the solution i think. The error was that SCK was not assigned to the output pin, it is needed cause i refer my delay loop from this point! Now the feedback scheme is indeed better then the normal scheme. Unfortunatly margins are still marginal :cry: 

create_generated_clock -name SCK -source  -invert

I'm happy to receive comments and thoughts.