Timing constraints for a feedback clock system

Your timing report doesn't look like the diagram. I don't see where/how Sck leaves the FPGA. The one with feedback correctly shows that feedback clock for latching the data, but never shows the clock that launches the data(SCK) leaving the FPGA.

The .sdc has a generated clock for SCK that looks correct. I'm wondering if you get a warning in TimeQuest about being unable to calculate latency to generated clock? THis occurs when it can't find a connection between the -source and the target. Usually this occurs if there is a ripple-clock(toggle FF?) on the path going out, in which case that register needs a generated clock too.