Timing constrain between pll clock and clock divisor

First, do you have paths between the 20MHz input clock and any of those outputs? If not, then it makes no difference if you put it in a group or not. All your doing is cutting non-existent paths. By default TQ will analyze all paths between the input clock and any of those PLL output clocks. If there are clocks that have funky relaitonships, such as 48MHz <=> 20MHz, you'll probably end up with a tiny setup relationship, the path will fail, and you then need to decide whether to modify the path so it doesn't exist or cut it some how(either with a set_false_path, or putting the clocks in different groups of a set_clock_groups assignment).

So:

a) In most designs, the reference clock only feeds the PLL and no logic directly, so there are not paths between it's logic(since it doesn't drive logic) and other domains. So it makes no difference.

b) Some users don't like to put it in there so in case someone uses it to drive logic that erroneously feeds another domain, it hopefully fails timing and they can fix it. Some users like to put it in there so it more clearly shows what clock(s) it is related to and not related to. If it's not explicitly cutting paths, it's user preference.

c) If you do have paths, especially asynchronous paths to other other domains that you want TQ to ignore, then you do want to put it in there(or cut those paths with set_false_path).