timing closure problem.

Hi Rysc,

Thank you for your reply. Yeah, they are actually nets in the design and it's in a clocked process. m, n, and h are synchronous integar signals produced outside the process with specific ranges (m: 0-8, n: 03, h: 0-183).

Yeah, m, n are the same for both sides of the equation.... hmmm... using 36 9-bit adders is an interesting idea if it doesn't use too much resources... I still have to control which adder to add and which register to output though (which means we need mux again... probably less).

Thanks again, I will give it a thought.

Hua