Timing Closure, LogicLock and Incremental Compilation

Hi guys,

There is something that I do not quite understand in design partitions. Let's say I have partitions for modules A, B and C where I am only interested in having a clean timing for A and B. So I set module A and B to 'Post-Synthesis' and module C to 'Empty'. However, after compilation, I can still locate the primitives of module C in Chip Planner and also in Timequest Timing report. Isn't this module supposed to be 'bypassed' since it was set to empty?

Another question is that let's say I have A meeting timing now. So I now changed it to post-fit while B still at post-syn, hoping to preserve the timing of module A. After I re-fit the project, I notice that module A's timing got worse. This doesnt seem to match with the concept of Incremental Compilation where the results are preserved. Anything that could've done wrong?