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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Timing analyzer warning related to signaltap

Hello Intel forums I have a project in Quartus prime pro 18.1 which has a signaltap instance. When I compile, I get these warnings during the timing analysis: Warning(332182): No path is found sat...
bitwise's avatar
bitwise
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

The ignored SDC was constraining skew across a group of signals, but the specific signals don't exist in your design. The assignment is thus ignored, and since the specified signals don't exist the fact that they won't have constrained skew is innocuous. If you open the Timequest GUI and run the diagnostic report to tell you what constraints were ignored then it should tell you if this ignored constraint was in your SDC file or embedded in HDL.