Timing Analyzer: Top Failing Paths

@sstrell I have a new theory!

I copied the generated vJTAG module from my Cyclone IV project to the Cyclone V project.

When creating a new vJTAG module, it asks for the device that it is intended for. Could it be that the one generated for the Cyclone IV is not truly compatible with the Cyclone V?

I just created a brand new project, added a VJTag and 100Mhz PLL clock same as in the example above: No problems with the timings whatsoever in Top Failing Paths

So I guess in future I should be regenerating any IP Core components when I move between different FPGA hardware platforms?