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SparkyNZ's avatar
SparkyNZ
Icon for Contributor rankContributor
3 years ago
Solved

Timing Analyzer: Top Failing Paths

Can somebody please help me. I am getting unpredictable behaviour with my design so I have been looking at the Top Failing Paths report. This appears to be full of SignalTap timing issues? What d...
  • SparkyNZ's avatar
    SparkyNZ
    3 years ago

    @sstrell I have a new theory!

    I copied the generated vJTAG module from my Cyclone IV project to the Cyclone V project.

    When creating a new vJTAG module, it asks for the device that it is intended for. Could it be that the one generated for the Cyclone IV is not truly compatible with the Cyclone V?

    I just created a brand new project, added a VJTag and 100Mhz PLL clock same as in the example above: No problems with the timings whatsoever in Top Failing Paths

    So I guess in future I should be regenerating any IP Core components when I move between different FPGA hardware platforms?

SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

Paul,


Glad you are able to resolve it. Yes, IP generation should be run every time there is changes in component, device and etc. To avoid any issue on timing and compatibility.

Let me know if there is any other concern.