Timing Analyzer strange behavior?

Good questions — both of these situations are common and worth understanding clearly.

"None Detected" in Timing Closure Recommendations

The Report Timing Closure Recommendations task in the Timing Analyzer analyzes paths and provides specific recommendations based on path characteristics. Intel® Quartus® Prime Standard Edition User Guide: Design Optimization The reports give you the most probable causes of failure for each analyzed path, and show recommendations that may help you fix the failing paths. Intel® Quartus® Prime Standard Edition User Guide: Design Optimization

"None Detected" simply means the tool didn't find any of the specific known patterns it checks for (e.g., excessive logic depth, high fanout, missing constraints, placement issues, etc.) on that particular path. The path is still genuinely failing — the tool just isn't able to attribute the failure to one of its recognized root-cause categories. In this situation, the Timing Optimization Advisor gives more general recommendations to improve timing performance for the design Intel® Quartus® Prime Standard Edition User Guide: Design Optimization and is worth running as a complement. You can also dig deeper manually:

• Calculating the intrinsic margin of a timing path, and then comparing that margin to other delays of the path, can help identify the specific reasons why a path fails its timing requirement. Report Timing Enable Extra Info → All in the Report Timing dialog to see the Setup Slack Breakdown.
• Viewing critical paths in the Chip Planner shows why a specific path is failing. You can see if any modification in the placement can reduce the negative slack. To display paths in the floorplan, perform a timing analysis and display results on the Timing Analyzer. Quartus® Prime Pro Edition User Guide

Same FROM/TO nodes showing both negative and positive slack

This is expected behavior and doesn't indicate an error in the tool. During analysis, the Timing Analyzer examines the timing paths in the design, calculates the propagation delay along each path, checks for timing constraint violations, and reports timing results as positive slack or negative slack. Negative slack indicates a timing violation. Positive slack indicates that timing requirements are met. Step 4: Analyze Timing Reports

The reason the same endpoint pair can show both values is that there are multiple distinct timing paths between those two nodes. The Timing Analyzer's report_timing command reports each path individually. The path with –1.572 ns is the worst-case (critical) route between those nodes under the setup analysis — that one is failing. The path with +2.928 ns is a different route through the fabric between the same source and destination registers, or it reflects a different launch/latch edge combination (for example, a different clock phase or a hold check on the same register pair). To perform a clock setup check, the Timing Analyzer determines a setup relationship by analyzing each launch and latch edge for each register-to-register path. For each latch edge at the destination register, the Timing Analyzer uses the closest previous clock edge at the source register as the launch edge. Clock Setup Analysis Different edge pairs naturally produce different slack values for the same physical register pair.

The actionable item is the path with –1.572 ns. Focus your optimization effort there — focus on improving the paths that show the worst slack. The Fitter works hardest on paths with the worst slack. If you fix these paths, the Fitter might be able to improve the other failing timing paths in the design. Tips for Analyzing Failing Paths

For the io_mcu_fpga_if_data → mif_controller_prefetch path where "None Detected" is shown, also verify that the SDC constraints on the v_clk_mif_in / PLL output clocks are correct — when the Timing Analyzer reports failing paths, verify if the failing requirements are correct. By default, the Timing Analyzer handles all clock domains as related, and this can cause some invalid requirements. To correct this condition, group clocks in your design appropriately. Resolving Common Timing Issues

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